The present invention relates generally to integrated circuit (chip) design, and more specifically, to synthesis of a logical chip design to a physical design. More specifically, the present invention provides performing automated component placement in a hierarchically-defined semiconductor design.
As integrated circuits increase in complexity and functionality, it becomes increasingly useful to adopt a hierarchical approach to their design. A “hierarchical” design is a unit-level design (i.e., the design of the entire circuit—the “unit”—as a whole) is divided into smaller-scale “macro elements,” which are themselves composed of smaller, lower-level components or “cells” (which, themselves, may be comprised of even smaller, lower-level components). Hierarchical design aids in the organization of the design process and also helps to avoid unnecessary duplication of work, since a typical circuit design will likely contain multiple copies of a single macro element and will usually contain multiple copies of a single cell.